EP2AGX95EF29C6N Datasheet, PDF (142/380 Pages) Altera Corporation – Device Interfaces and Integration

5–34
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–30 shows an example waveform of the phase relationship between the PLL
clocks in external feedback mode.
Figure 5–30. Phase Relationship Between the PLL Clocks in External Feedback Mode for Arria II Devices
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at
the Register
Clock Port (1)
Dedicated PLL
Clock Outputs (1)
fbin Clock Input Pin
Note to Figure 5–30:
(1) The PLL clock outputs can lead or lag the fbin clock input.
Figure 5–31 shows external feedback mode implementation in Arria II GZ devices.
Figure 5–31. External Feedback Mode in Arria II GZ Devices
inclk
÷n
PFD CP/LF VCO
÷C0
÷C1
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
fbout
÷m
fbin
external
board
trace
Clock Multiplication and Division
Each Arria II PLL provides clock synthesis for PLL output ports with
M/(N  post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor (n) and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f_in (M/N). Each output port has a unique post-scale counter that
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies
that meets its frequency specifications. For example, if output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz in the VCO range). Then the post-scale
counters scale down the VCO frequency for each output port.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation