English
Language : 

EP2AGX95EF29C6N Datasheet, PDF (77/380 Pages) Altera Corporation – Device Interfaces and Integration
December 2010
AIIGX51004-4.0
AIIGX51004-4.0
4. DSP Blocks in Arria II Devices
This chapter describes how the dedicated high-performance digital signal processing
(DSP) blocks in Arria II device are optimized to support DSP applications requiring
high data throughput, such as finite impulse response (FIR) filters, infinite impulse
response (IIR) filters, fast Fourier transform (FFT) functions, and encoders. You can
configure the DSP blocks to implement one of several operational modes to suit your
application. The built-in shift register chain, multipliers, and adders/subtractors
minimize the amount of external logic to implement these functions, resulting in
efficient resource utilization and improved performance and data throughput for DSP
applications.
These DSP blocks are the fourth generation of hardwired, fixed-function silicon blocks
dedicated to maximizing signal processing capability and ease-of-use at the lowest
silicon cost.
Many complex systems, such as WiMAX, 3GPP WCDMA, high-performance
computing (HPC), voice over Internet protocol (VoIP), H.264 video compression,
medical imaging, and HDTV, use sophisticated DSP techniques. Arria II devices are
ideally suited for these systems because the DSP blocks consist of a combination of
dedicated elements that perform multiplication, addition, subtraction, accumulation,
summation, and dynamic shift operations.
Along with the high-performance Arria II soft logic fabric and memory structures,
you can configure DSP blocks to build sophisticated fixed-point and floating-point
arithmetic functions. These can be manipulated easily to implement common, larger
computationally intensive subsystems such as FIR filters, complex FIR filters, IIR
filters, FFT functions, and discrete cosine transform (DCT) functions.
This chapter contains the following sections:
■ “DSP Block Overview” on page 4–2
■ “Simplified DSP Operation” on page 4–4
■ “Operational Modes Overview” on page 4–7
■ “DSP Block Resource Descriptions” on page 4–8
■ “Arria II Operational Mode Descriptions” on page 4–14
■ “Software Support for Arria II Devices” on page 4–31
© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
Subscribe