EP2AGX95EF29C6N Datasheet, PDF (197/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
Termination Schemes for I/O Standards
6–33
Differential LVPECL
Arria II devices support the LVPECL I/O standard on input clock pins only. LVPECL
output operation is not supported. LVDS input buffers are used to support LVPECL
input operation. AC-coupling is required when the LVPECL common mode voltage of
the output buffer is higher than Arria II LVPECL input common mode voltage.
Figure 6–16 shows the AC-coupled termination scheme. The 50- resistors used at the
receiver end are external to the device.
Figure 6–16. LVPECL AC-Coupled Termination
LVPECL
Output Buffer
Arria II
LVPECL Input Buffer
0.1 μF
Z_O
Z_O
0.1 μF
V_ICM
Arria II devices support DC-coupled LVPECL if the LVPECL output common mode
voltage is within the Arria II LVPECL input buffer specification (Figure 6–17).
Figure 6–17. LVPECL DC-Coupled Termination
LVPECL
Output Buffer
Arria II
LVPECL Input Buffer
Z_O = 50 Ω
Z_O = 50 Ω
100 Ω
RSDS
Arria II devices supports true RSDS, RSDS with a one-resistor network, and RSDS
with a three-resistor network. Two single-ended output buffers are used for external
one- or three-resistor networks, as shown in Figure 6–18. Only Arria II GZ row I/O
banks support RSDS output using true LVDS output buffers without an external
resistor network.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration