EP2AGX95EF29C6N Datasheet, PDF (160/380 Pages) Altera Corporation – Device Interfaces and Integration

5–52
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Table 5–21. Dynamic Phase-Shifting Control Signals for Arria II Devices (Part 2 of 2)
Signal Name
Description
Source
Destination
SCANCLK
PHASEDONE
Free running clock from core used in
combination with PHASESTEP to enable,
disable, or both dynamic phase shifting. Shared
with scanclk for dynamic reconfiguration.
When asserted, this indicates to the core logic
that the phase adjustment is complete and the
PLL is ready to act on a possible second
adjustment pulse. Asserts based on internal
PLL timing. Deasserts on the rising edge of
scanclk.
GCLK, RCLK, or
I/O pin
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
Logic array or I/O
pins
Table 5–22 lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECT setting.
Table 5–22. Phase Counter Select Mapping for Arria II Devices (Note 1)
PHASECOUNTERSELECT[3]
[2]
[1]
[0]
Selects
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
Note to Table 5–22:
(1) C7 to C9 counter are only available for Arria II GZ devices.
All Output Counters
M Counter
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
C5 Counter
C6 Counter
C7 Counter
C8 Counter
C9 Counter
To perform one dynamic phase-shift, follow these steps:
1. Set PHASEUPDOWN and PHASECOUNTERSELECT as required.
2. Assert PHASESTEP for at least two SCANCLK cycles. Each PHASESTEP pulse allows one
phase shift.
3. Deassert PHASESTEP after PHASEDONE goes low.
4. Wait for PHASEDONE to go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple
phase-shifts.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation