EP2AGX95EF29C6N Datasheet, PDF (116/380 Pages) Altera Corporation – Device Interfaces and Integration

5–8
Figure 5–8. PCLK Networks in Arria II GZ Devices
CLK[12..15]
T1
T2
PCLK[0..10]
PCLK[11..21]
L2
CLK[0..3]
L3
PCLK[22..32]
Q1 Q2
Q4 Q3
PCLK[33..43]
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
PCLK[77..87]
PCLK[66..76]
PCLK[55..65]
R2
CLK[8..11]
R3
PCLK[44..54]
B1
B2
CLK[4..7]
[
Clock Sources Per Quadrant
There are 26 section clock (SCLK) networks available in each spine clock that can
drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and
three core reference clocks. SCLKs are the clock resources to the core functional
blocks, PLLs, and I/O interfaces of the device.
Figure 5–9 shows that the GCLK, RCLK, PCLK, or PLL feedback clock networks in
each spine clock can drive the SCLKs.
Figure 5–9. Hierarchical Clock Networks per Spine Clock in Arria II Devices (Note 1)
GCLK
PLL feedback clock (2)
PCLK
RCLK
16
3
16 (3)
22 (4)
SCLK 26
9
Column I/O clock (5)
2
Core reference
clock (6)
6
Row clock (7)
Notes to Figure 5–9:
(1) The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. The total number of clock
resources must not exceed the SCLK limits in each region to ensure successful design fitting in the Quartus^® II
software.
(2) There are up to three PLL feedback clocks which are from the PLL that drives into the SCLKs.
(3) There are up to 16 PCLKs that can drive the SCLKs in each spine clock in the largest device.
(4) There are up to 22 RCLKs (Arria II GZ) or 12 RCLKs (Arria II GX) that can drive the SCLKs in each spine clock in the
largest device.
(5) The column I/O clock drives the column I/O core registers and I/O interfaces.
(6) The core reference clock feeds into the PLL as the PLL reference clock.
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation