EP2AGX95EF29C6N Datasheet, PDF (294/380 Pages) Altera Corporation – Device Interfaces and Integration

9–8
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Configuration Process
A reconfiguration is initiated by toggling the nCONFIG pin from high to low and then
back to high with a minimum t_CFG low-pulse width either in the configuration,
configuration error, initialization, or user mode stage. When nCONFIG is pulled low,
nSTATUS and CONF_DONE are also pulled low and all the I/O pins are tri-stated. After
nCONFIG and nSTATUS return to a logic-high level, configuration begins.
A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when
the external host (a Max® II CPLD or a microcontroller) is not driving the line. For
example, during external host reprogramming or power-up where the I/O driving
nCONFIG may be tri-stated). If a pull-up resistor is added to the nCONFIG line, the FPGA
stays in user mode if the external host is being reprogrammed. If a pull-down resistor
is added to the nCONFIG line, the FPGA goes into reset mode if the external host is
being reprogrammed. Whenever the nCONFIG line is released high, ensure the first
DCLK and DATA are not driven unintentionally.
1 Altera recommends to keep the nCONFIG line low if the external host or the FPGA is
not ready for configuration.
Configuration Error
If an error occurs during configuration, Arria II devices assert the nSTATUS signal low,
indicating a data frame error; the CONF_DONE signal stays low. If you turn on the
Auto-restart configuration after error option (available in the Quartus II software
from the General tab of the Device and Pin Options dialog box), the Arria II device
resets the configuration device and retries the configuration. If you turn off this
option, the system must monitor nSTATUS for errors and then pulse nCONFIG low to
restart the configuration.
Initialization
In Arria II devices, the initialization clock source is either the internal oscillator or the
optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II device provides itself with
enough clock cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. After all the configuration data is
accepted and CONF_DONE goes high, CLKUSR is enabled after the time specified as
t_CD2CU. After this time period elapses, Arria II devices require a minimum number of
clock cycles to initialize properly and enter user mode as specified in the t_CD2UMC
parameter.
1 Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed bitstream in the
FPP or PS configuration mode.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation