EP2AGX95EF29C6N Datasheet, PDF (36/380 Pages) Altera Corporation – Device Interfaces and Integration

2–6
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
Figure 2–6 shows a detailed view of all the connections in an ALM.
Figure 2–6. Connection Details of the Arria II ALM
shared_arith_in
carry_in
syncload
aclr[1:0]
clk[2:0] sclr
reg_chain_in
dataf0
datae0
dataa
datab
datac0
4-INPUT
LUT
GND
+
3-INPUT
LUT
CLR
D
Q
3-INPUT
LUT
local
interconnect
row, column
direct link routing
row, column
direct link routing
datac1
datae1
dataf1
4-INPUT
LUT
3-INPUT
LUT
3-INPUT
LUT
+
V_CC
CLR
D
Q
local
interconnect
row, column
direct link routing
row, column
direct link routing
shared_arith_out
carry_out
reg_chain_out
One ALM contains two programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, and synchronous load and clear inputs.
Global signals, general purpose I/O (GPIO) pins, or any internal logic can drive the
register’s clock and clear-control signals. Either GPIO pins or internal logic can drive
the clock enable. For combinational functions, the register is bypassed and the output
of the LUT drives directly to the outputs of an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive the ALM outputs (refer to
Figure 2–6). For each set of output drivers, two ALM outputs can drive column, row,
or direct link routing connections, and one of these ALM outputs can also drive local
interconnect resources. The LUT or adder can drive one output while the register
drives another output.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation