EP2AGX95EF29C6N Datasheet, PDF (258/380 Pages) Altera Corporation – Device Interfaces and Integration

8–12
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
The Arria II PLL receives the external reference clock input (rx_inclock) and
generates eight different phases of the same clock. The DPA block chooses one of the
eight clock phases from the center/corner PLL and aligns to the incoming data to
maximize receiver skew margin. The synchronizer circuit is a 1-bit wide by 6-bit deep
FIFO buffer that compensates for any phase difference between the DPA block and the
deserializer. If necessary, the user-controlled data realignment circuitry inserts a single
bit of latency in the serial bit stream to align to the word boundary. The deserializer
converts the serial data to parallel data and sends the parallel data to the FPGA fabric.
The physical medium connecting the LVDS transmitter and the receiver channels may
introduce skew between the serial data and the source synchronous clock. The
instantaneous skew between each LVDS channel and the clock also varies with the
jitter on the data and clock signals, as seen by the receiver.
1 Only non-DPA mode requires manual skew adjustment.
Arria II devices support the following receiver modes to overcome skew between the
source-synchronous or reference clock and the received serial data:
■ Non-DPA mode
■ DPA mode
■ Soft clock data recovery (CDR) mode
1 Dedicated SERDES and DPA circuitry only exist on the right side of the device. Top
and bottom I/O banks only support non-DPA mode, in which the SERDES are
implemented in the core logic.
Receiver Hardware Blocks
The differential receiver has the following hardware blocks:
■ “DPA” on page 8–12
■ “Synchronizer” on page 8–13
■ “Data Realignment Block (Bit Slip)” on page 8–14
■ “Deserializer” on page 8–15
DPA
The DPA block takes in high-speed serial data from the differential input buffer and
selects the optimal phase from one of the eight clock phases generated by the PLL to
sample the data. The eight phases of the clock are equally divided, giving a 45°
resolution. The maximum phase offset between the received data and the selected
phase is 1/8 unit interval (UI), which is the maximum quantization error of the DPA
block. The optimal clock phase selected by the DPA block (DPA_diffioclk) is also
used to write data into the FIFO buffer or to clock the SERDES for soft-CDR operation.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation