EP2AGX95EF29C6N Datasheet, PDF (168/380 Pages) Altera Corporation – Device Interfaces and Integration

6–4
Chapter 6: I/O Features in Arria II Devices
I/O Standards Support
Table 6–2. I/O Standards and Voltage Levels for Arria II GZ Devices (Note 1) (Part 2 of 2)
I/O Standard
Standard
Support
V_CCIO (V)
Input Operation
Output Operation
Column
Row
Column
Row
I/O Banks I/O Banks I/O Banks I/O Banks
V_CCPD (V)
(Pre-
Driver
Voltage)
V_REF (V)
(Input
Ref
Voltage)
V_TT (V)
(Board
Termination
Voltage)
LVDS (4), (5), (8)
ANSI/TIA/
EIA-644
(2)
(2)
2.5
2.5
2.5
—
—
RSDS (6), (7), (8)
—
(2)
(2)
2.5
2.5
2.5
—
—
mini-LVDS (6), (7),
(8)
—
(2)
(2)
2.5
2.5
2.5
—
—
LVPECL
—
(4)
2.5
—
—
2.5
—
—
Notes to Table 6–2:
(1) V_CCPD is either 2.5 or 3.0 V. For V_CCIO = 3.0 V, V_CCPD = 3.0 V. For V_CCIO = 2.5 V or less, V_CCPD = 2.5 V.
(2) Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by V_CCPD. Row I/O banks support both true differential input
buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers. I/O pins
are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without
R_D OCT support.
(3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Arria II devices, refer to “3.3-V I/O Interface” on page 6–13.
(4) Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/Os are powered by V_CCCLKIN when configured
as differential clock inputs. They are powered by V_CCIO when configured as single-ended clock inputs. Differential clock inputs in row I/Os are powered
by V_CCPD.
(5) Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a three-resistor
(LVDS_E_3R) network.
(6) Row I/O banks support RSDS and mini-LVDS I/O standards using a true LVDS output buffer without a resistor network.
(7) Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R and
mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
(8) The emulated differential output standard that supports the tri-state feature includes: LVDS_E_1R, LVDS_E_3R, RSDS_E_1R, RSDS_E_3R,
Mini_LVDS_E_1R, and Mini_LVDS_E_3R. For more information, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide.
f For detailed electrical characteristics of each I/O standard, refer to the Device
Datasheet for Arria II Devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation