EP2AGX95EF29C6N Datasheet, PDF (299/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
9–13
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. Arria II devices support an f_MAX of
125 MHz.
Figure 9–2 shows how to configure multiple Arria II devices using a MAX II device.
This circuit is similar to the FPP configuration circuit for a single device, except the
Arria II devices are cascaded for multi-device configuration.
Figure 9–2. Multi-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
(1) (1) (2)
10 kΩ
10 kΩ 10 kΩ
External Host
(MAX II Device or
GND
Microprocessor)
Arria II Device 1
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(1)
(3)
10 kΩ
DATA[7..0]
nCONFIG
DCLK
Arria II Device 2
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(3)
N.C.
DATA[7..0]
nCONFIG
DCLK
Notes to Figure 9–2:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V_CCIO pin.
For Arria II GZ devices, use the V_CCPGM pin. V_CCIO/V_CCPGM must be high enough to meet the V_IH specification of the I/O on both the device and the
external host. Altera recommends powering up the configuration system I/Os with V_CCIO/V_CCPGM.
(2) A pull-up resistor to V_CCIO/V_CCPGM or a pull-down resistor keeps the nCONFIG line in a known state when the external host is not driving the line.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts the
second device to begin configuration. The second device in the chain begins
configuration in one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device or microprocessor. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. The configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration