EP2AGX95EF29C6N Datasheet, PDF (205/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
7–3
Memory Interfaces Pin Support for Arria II Devices
Figure 7–2. External Memory Interface Datapath Overview for Arria II GZ Devices (Note 1), (2)
Arria II GZ FPGA
DQS Logic
DLL
Block
Memory
DQS (Read) (3)
DPRAM
Postamble Enable
Postamble Clock
Postamble
Control
Circuit
4n
2n
2n
Half Data Rate
Input Registers
Synchronization
Registers
DQS Enable
Circuit
DDR Input
Registers
Resynchronization Clock
4n
2n
Half Data Rate
Output Registers
DDR Output
and Output
Enable
Registers
n
DQ (Read) (3)
n
DQ (Write) (3)
Clock
Management
and Reset
Half-Rate Resynchronization Clock
DQ Write Clock
Half-Rate Clock
DQS Write Clock
4
Half Data Rate
Output Registers
2
DDR Output
and Output
Enable
Registers
DQS (Write) (3)
Notes to Figure 7–2:
(1) You can bypass each register block.
(2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Arria II GZ IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
and write operations.
Memory Interfaces Pin Support for Arria II Devices
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM or BWSn) pins to enable write masking. This section describes how Arria II
devices support all these pins.
1 If you have more than one clock pair, you must place them in the same DQ group. For
example, if you have two clock pairs, you must place both of them in the same ×4
DQS group.
f For more information about pin connections, refer to the Arria II Device Family Pin
Connection Guidelines.
The DDR3, DDR2, DDR SDRAM, and RLDRAM II devices use CK and CK# signals to
capture the address and command signals. You can generate these signals to mimic
the write-data strobe with Arria II DDR I/O registers (DDIOs) to ensure that timing
relationships between the CK/CK# and DQS signals (t_DQSS, t_DSS, and t_DSH in DDR3,
DDR2, and DDR SDRAM devices) are met. The QDR II+/QDR II SRAM devices use
the same clock (K/K#) to capture the write data, address, and command signals.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration