EP2AGX95EF29C6N Datasheet, PDF (153/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–45
f For more information about the PLL reconfiguration port signals, refer to the Phase
Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide.
1 The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, all counters are not simultaneously updated.
To reconfigure the PLL counters, follow these steps:
1. Assert the SCANCLKENA signal at least one SCANCLK cycle prior to shifting in the first
bit of SCANDATA (Dn for Arria II GX devices or D0 for Arria II GZ devices).
2. Serial data (SCANDATA) is shifted into the scan chain on the second rising edge of
SCANCLK.
3. For Arria II GX devices, after all 180 bits are scanned into the scan chain, the
SCANCLKENA signal is deasserted to prevent inadvertent shifting of bits in the scan
chain. For Arria II GZ devices, after all 234 bits (top and bottom PLLs) or 180 bits
(left and right PLLs) have been scanned into the scan chain, the SCANCLKENA signal
is deasserted to prevent inadvertent shifting of bits in the scan chain.
4. The CONFIGUPDATE signal is asserted for one SCANCLK cycle to update the PLL
counters with the contents of the scan chain.
5. The SCANDONE signal goes high indicating the PLL is being reconfigured. A falling
edge indicates the PLL counters are updated with new settings.
6. Reset the PLL with the ARESET signal if you make any changes to the M, N, or
post-scale output C counters or the Icp, R, or C settings.
7. Repeat steps 1 through 5 to reconfigure the PLL any number of times.
Figure 5–40 shows a functional simulation of the PLL reconfiguration feature.
Figure 5–40. PLL Reconfiguration Waveform for Arria II Devices
SCANDATA
Dn
D0
SCANCLK
SCANCLKENA
SCANDATAOUT
Dn_old
D0_old Dn
CONFIGUPDATE
SCANDONE
ARESET
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration