EP2AGX95EF29C6N Datasheet, PDF (232/380 Pages) Altera Corporation – Device Interfaces and Integration

7–30
Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Table 7–8. DLL Reference Clock Input for EP2AGZ225, EP2AGZ300, and EP2AGZ350 Devices in the 1152-Pin FineLine
BGA Package (Part 2 of 2)
DLL
DLL2
DLL3
CLKIN (Top/Bottom)
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
CLKIN (Left/Right)
CLK10P
CLK11P
CLK10P
CLK11P
PLL (Top/Bottom)
PLL_B2
PLL_T2
PLL (Left/Right)
—
PLL_R2
PLL (Corner)
—
—
Table 7–9. DLL Reference Clock Input for EP2AGZ225, EP2AGZ300, and EP2AGZ350 Devices in the 1517-Pin FineLine
BGA Package
DLL
CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right)
PLL (Corner)
CLK12P
CLK0P
CLK13P
CLK1P
DLL0
PLL_T1
PLL_L2
—
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
DLL1
CLK5P
CLK6P
CLK1P
PLL_B1
PLL_L3
—
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
DLL2
CLK5P
CLK9P
PLL_B2
PLL_R3
—
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
DLL3
PLL_T2
PLL_R2
—
CLK14P
CLK10P
CLK15P
CLK11P
1 If you use the ALTMEMPHY megafunction or UniPHY IP core, Altera recommends
using the dedicated PLL input pin for the PLL reference clock.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation