EP2AGX95EF29C6N Datasheet, PDF (187/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
OCT Support
6–23
R_D OCT for Arria II LVDS Input I/O Standard
All I/O banks in Arria II GX devices support input R_D OCT with a nominal resistance
value of 100 , as shown in Figure 6–7. However, not all input differential pins
support R_D OCT. You can enable R_D OCT when both the V_CCIO and V_CCPD is set to
2.5 V.
Arria II GZ column I/O banks and dedicated clock input pairs on the row I/O banks
do not support R_D OCT. You can enable the Arria II GZ R_D OCT in row I/O banks
when both the V_CCIO and V_CCPD is set to 2.5 V.
Figure 6–7. Differential Input On-Chip Termination for Arria II Devices
Transmitter
Receiver
Z_O = 50 Ω
Z_O = 50 Ω
100 Ω
f For more information about R_D OCT, refer to the High-Speed Differential I/O Interfaces
and DPA in Arria II Devices chapter.
R_T OCT with Calibration for Arria II GZ Devices
Arria II GZ devices support R_T OCT with calibration in all banks. R_T OCT with
calibration is only supported for input configuration of input and bidirectional pins.
Output pin configurations do not support R_T OCT with calibration. Figure 6–8 shows
R_T OCT with calibration. When you use R_T OCT, the V_CCIO of the bank must match the
I/O standard of the pin where the R_T OCT is enabled.
Figure 6–8. R_T OCT with Calibration for Arria II GZ Devices
Arria II GZ OCT
V_CCIO
Z_O = 50 
V_REF
100 
100 
Transmitter
GND Receiver
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration