EP2AGX95EF29C6N Datasheet, PDF (328/380 Pages) Altera Corporation – Device Interfaces and Integration

9–42
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Device Configuration Pins
Table 9–16. Dedicated Configuration Pins on the Arria II Device (Part 3 of 4)
Pin Name
nCE
nCEO
ASDO (2)
nCSO (2)
DCLK (2)
User Mode
Configuration
Scheme
Pin Type
Description
Active-low chip enable. The nCE pin activates the device with
a low signal to allow configuration. The nCE pin must be held
low during configuration, initialization, and user mode. In
single device configuration, it must be tied low. In
N/A
All
Input ^{multi-device configuration, nCE of the first device is tied low}
while its nCEO pin is connected to nCE of the next device in
the chain.
The nCE pin must also be held low for successful JTAG
programming of the device.
Output that drives low when device configuration is
complete. In a single-device configuration, this pin is left
floating. In a multi-device configuration, this pin feeds the
next device’s nCE pin and is pulled high by an external 10-k
resistor. The nCEO of the last device in the chain is left
I/O
All
Output _floating.
open-drain _{The nCEO pin is powered by VCCIO for Arria II GX devices and}
V_CCPGM for Arria II GZ devices.
After configuration, nCEO is available as user I/O pins. The
state of the nCEO pin depends on the Dual-Purpose Pin
settings.
Control signal from the Arria II device to the serial
configuration device in AS mode used to read out
N/A
AS
Output ^{configuration data.}
In AS mode, ASDO has an internal pull-up resistor that is
always active.
Output control signal from the Arria II device to the serial
configuration device in AS mode that enables the
N/A
AS
Output ^{configuration device.}
In AS mode, nCSO has an internal pull-up resistor that is
always active.
In PS and FPP configurations, DCLK is the clock input used
to clock data from an external source into the target device.
Data is latched into the device on the rising edge of DCLK.
In AS mode, DCLK is an output from the Arria II device that
N/A
Synchronous
configuration
schemes
(PS, FPP, AS)
Input
(PS, FPP)
Output (AS)
provides timing for the configuration interface. In AS mode,
DCLK has an internal pull-up resistor (typically 25 k) that is
always active.
After configuration, this pin by default is driven into an
inactive state. In schemes that use a control host, DCLK must
be driven either high or low, whichever is more convenient.
Toggling this pin after configuration does not affect the
configured device.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation