EP2AGX95EF29C6N Datasheet, PDF (270/380 Pages) Altera Corporation – Device Interfaces and Integration

8–24
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Source-Synchronous Timing Budget
Figure 8–21. Bit Order and Word Boundary for One Differential Channel (Note 1)
Transmitter Channel
Operation (x8 Mode)
tx_outclock
Previous Cycle
Current Cycle
Next Cycle
tx_out X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X
MSB
LSB
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X
rx_outclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
Note to Figure 8–21:
(1) These waveforms are only functional waveforms and are not intended to convey timing information.
3210XXXX
Table 8–8 lists the conventions for differential bit naming for 18 differential channels.
The MSB and LSB positions increase with the number of channels used in a system.
Table 8–8. Differential Bit Naming
Receiver Channel Data
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Internal 8-Bit Parallel Data
MSB Position
7
15
23
31
39
47
55
63
71
79
87
95
103
111
119
127
135
143
LSB Position
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
136
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation