EP2AGX95EF29C6N Datasheet, PDF (207/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
7–5
Memory Interfaces Pin Support for Arria II Devices
The DQ and DQS pin locations are fixed in the pin table. Memory interface circuitry is
available in every Arria II I/O bank that does not support transceivers. All memory
interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, QDR II+ and QDR II SRAM, and RLDRAM II devices.
Arria II devices support DQ and DQS signals with DQ bus modes of ×4, ×8/×9,
×16/×18, or ×32/×36, although not all devices support DQS bus mode in ×32/×36.
The DDR, DDR2, and DDR3 SDRAM interfaces use one DQS pin for each ×8 group;
for example, an interface with a ×72 wide interface requires nine DQS pins. When any
of these pins are not used for memory interfacing, you can use these pins as user I/Os.
Additionally, you can use any DQSn or CQn pins not used for clocking as DQ (data)
pins.
Table 7–1 lists pin support per DQ/DQS bus mode, including the DQS/CQ and
DQSn/CQn pin pair, for Arria II devices.
Table 7–1. DQ/DQS Bus Mode Pins for Arria II Devices
Mode
DQSn Support
CQn Support
Parity or DM
(Optional)
QVLD
(Optional) (1)
Typical
Number of
Data Pins per
Group
Maximum
Number of
Data Pins per
Group (2)
×4
Yes
No
No (6)
No
4
5
×8/×9 (3)
Yes
Yes
Yes
Yes
8 or 9
11
×16/×18 (4)
Yes
Yes
Yes
Yes
16 or 18
23
×32/×36 (5)
Yes
Yes
Yes
Yes
32 or 36
47
×32/×36 (7)
Yes
Yes
No (8)
Yes
32 or 36
39
Notes to Table 7–1:
(1) The QVLD pin is not used in the ALTMEMPHY megafunction and it is only applicable for Arria II GZ devices.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQ/DQS group in a particular device. Check the pin table for the exact number per group. For DDR3, DDR2,
and DDR interfaces, the number of pins is further reduced for an interface larger than ×8 due to the need of one DQS pin for each ×8/×9 group
that is used to form the x16/×18 and ×32/×36 groups.
(3) Two ×4 DQ/DQS groups are stitched to make a ×8/×9 group so there are a total of 12 pins in this group.
(4) Four ×4 DQ/DQS groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQ/DQS groups are stitched to make a ×32/×36 group.
(6) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(7) These ×32/×36 DQ/DQS groups are available in EP2AGZ300 and EP2AGZ350 devices in 1152- and 1517-pin FineLine BGA packages. There are
40 pins in each of these DQ/DQS groups.
(8) There are 40 pins in each of these DQ/DQS groups. You cannot place the BWSn pins within the same DQ/DQS group as the write data pins
because of insufficient pins availability.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration