EP2AGX95EF29C6N Datasheet, PDF (169/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
6–5
I/O Banks
I/O Banks
Arria II GX devices contain up to 16 I/O banks as shown in Figure 6–1. The left I/O
banks are dedicated for high-speed transceivers. Bank 3C and 8C are dedicated for
configuration pins. The rest of the banks are user I/O banks that support all
single-ended and differential I/O standards.
Figure 6–1. I/0 Banks in Arria II GX Devices (Note 1), (2), (3), (4), (5), (6), (7)
Bank 8C
Bank 8B
Bank 8A
Bank 7A
Bank 7B
These I/O Banks Support:
3.3-V LVTTL/LVCMOS, 3.0-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS, 1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS, 1.2-V LVCMOS,
True LVDS, Emulated LVDS, BLVDS, RSDS, mini-LVDS,
SSTL-2, SSTL-18, SSTL-15,
HSTL-18, HSTL-15, HSTL-12,
Differential SSTL-2, Differenital SSTL-18,
Differential SSTL-15, Differential HSTL-18,
Differential HSTL-15, and Differential HSTL-12
Bank 3C
Bank 3B
Bank 3A
Bank 4A
Bank 4B
Notes to Figure 6–1:
(1) Banks GXB0, GXB1, GXB2, and GXB3 are dedicated banks for high-speed transceiver I/Os.
(2) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.
(3) LVDS with DPA is supported at banks 5A, 5B, 6A, and 6B.
(4) Differential HSTL and SSTL inputs use LVDS differential input buffers without R_D OCT support.
(5) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(6) Figure 6–1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(7) The PLL_CLKOUT pin supports only emulated differential I/O standard but not true differential I/O standard.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration