EP2AGX95EF29C6N Datasheet, PDF (375/380 Pages) Altera Corporation – Device Interfaces and Integration

June 2011
AIIGX51012-3.1
AIIGX51012-3.1
12. Power Management in Arria II
Devices
This chapter describes the static and dynamic power of Arria^® II devices. Static power
is the power consumed by the FPGA when it is configured, but no clocks are
operating. Dynamic power is composed of switching power when the device is
configured and running.
The PowerPlay Power Analyzer in the Quartus^® II software optimizes all designs
with Arria II power technology to ensure performance is met at the lowest power
consumption. This automatic process allows you to concentrate on the functionality of
your design instead of the power consumption of your design.
f For more information about using the PowerPlay Power Analyzer in the Quartus II
software, refer to the Power Estimation and Power Analysis section in volume 3 of the
Quartus II Handbook.
This chapter includes the following sections:
■ “External Power Supply Requirements” on page 12–1
■ “Power-On Reset Circuitry” on page 12–1
■ “Hot Socketing” on page 12–2
External Power Supply Requirements
f For more information about the Arria II external power supply requirements and the
power supply pin connections, refer to the following:
■ For more information about Altera-recommended power supply operating
conditions, refer to the Device Datasheet for Arria II Devices chapter.
■ For more information about power supply pin connection guidelines and
power regulator sharing, refer to the Arria II Device Family Pin Connection
Guidelines.
Power-On Reset Circuitry
The Arria II power-on reset (POR) circuitry generates a POR signal to keep the device
in the reset state until the power supply’s voltage levels have stabilized during
power-up. The POR circuitry monitors V_CC, V_{CCA_PLL}, V_CCCB, V_CCPD, and V_CCIO
supplies for I/O banks 3C and 8C in Arria II GX devices, where the configuration pins
are located. The POR circuitry tri-states all user I/O pins until the power supplies
reach the recommended operating levels. These power supplies are required to
monotonically reach their full-rail values without plateaus and within the maximum
power supply ramp time (t_RAMP.). The POR circuitry de-asserts the POR signal after
the power supplies reach their full-rail values to release the device from the reset
state.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011
Subscribe