EP2AGX95EF29C6N Datasheet, PDF (129/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–21
Cascading PLLs
You can cascade the corner and center PLLs through the GCLK and RCLK networks
(Arria II GX devices) or left/right and top/bottom PLLs through the GCLK and
RCLK networks (Arria II GZ devices). In addition, where two PLLs exist next to each
other, there is a direct connection between them that does not require the GCLK and
RCLK network. By cascading PLLs, you can use this path to reduce clock jitter. For
Arria II GX devices, the direct PLL cascading feature is available in PLL_5 and PLL_6
on the right side of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
Arria II GX devices allow cascading of PLL_1 and PLL_4 to the transceiver PLLs (clock
management unit PLLs and receiver clock data recoveries [CDRs]). Arria II GZ
devices allows cascading the left and right PLLs to transceiver PLLs (CMU PLLs and
receiver CDRs).
If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth
setting, while the destination (downstream) PLL must have a high-bandwidth setting.
Ensure that there is no overlap of the bandwidth ranges of the two PLLs.
f For more information, refer to the “FPGA Fabric PLLs-Transceiver PLLs Cascading”
section in the Transceiver Clocking in Arria II Devices chapter.
f For more information about PLL cascading in external memory interfaces designs,
refer to the External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Guide.
PLLs in Arria II Devices
Arria II GX devices offer up to six PLLs per device and seven outputs per PLL, while
Arria II GZ devices offer up to eight PLLs that provide robust clock management and
synthesis for device clock management, external system clock management, and
high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical
location in the device floor plan. For the location and number of PLLs in Arria II
devices, refer to Figure 5–1 on page 5–4 through Figure 5–4 on page 5–6.
1 Depending on the package, Arria II GX devices offer up to eight transceiver
transmitter (TX) PLLs per device that can be used by the FPGA fabric if they are not
used by the transceiver.
f
For more information about the number of general-purpose and transceiver TX PLLs
in each device density, refer to the Overview for Arria II Device Family chapter. For more
information about using the transceiver TX PLLs in the transceiver block, refer to the
Transceiver Clocking in Arria II Devices chapter.
All Arria II PLLs have the same core analog structure and support features with
minor differences in the features that are supported for Arria II GZ devices.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration