EP2AGX95EF29C6N Datasheet, PDF (127/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
5–19
In Arria II devices, the clkena signals are supported at the clock network level instead
of at the PLL output counter level. This allows you to gate off the clock even when a
PLL is not used. You can also use the clkena signals to control the dedicated external
clocks from the PLLs. Arria II devices also have an additional metastability register
that aids in asynchronous enable or disable of the GCLK and RCLK networks. You
can optionally bypass this register in the Quartus II software.
Figure 5–17 shows a waveform example for the clock output enable. The clkena
signal is synchronous to the falling edge of the clock output.
Figure 5–17. clkena Signals for Arria II Devices
output of
clock
select multiplexer
clkena
output of AND
gate with R2 bypassed
output of AND
gate with R2 not bypassed
Note to Figure 5–17:
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL<#>_CLKOUT pins.
The PLL can remain locked independent of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low power or sleep mode. The clkena signal can also disable clock outputs if
the system is not tolerant of frequency over-shoot during resynchronization.
Clock Source Control for PLLs
The clock input to Arria II PLLs comes from clock input multiplexers. The clock
multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK
and RCLK networks, or from dedicated connections between adjacent corner and
center PLLs (Arria II GX devices) or from dedicated connections between adjacent
top/bottom and left/right PLLs (Arria II GZ devices). For Arria II GX devices, the
clock input sources to corner (PLL_1, PLL_2, PLL_3, PLL_4) and center PLLs (PLL_5 and
PLL_6) are shown in Figure 5–18. For Arria II GZ devices, the clock input sources to
top/bottom and left/right PLLs (L2, L3, T1, T2, B1, B2, R2, and R3) are shown in
Figure 5–19.
The multiplexer select lines are set in the configuration file only. When configured,
you cannot change this block without loading a new .sof or .pof. The Quartus II
software automatically sets the multiplexer select signals depending on the clock
sources selected in your design.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration