EP2AGX95EF29C6N Datasheet, PDF (75/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
Document Revision History
3–27
Document Revision History
Table 3–10 lists the revision history for this chapter.
Table 3–10. Document Revision History
Date
December 2011
June 2011
December 2010
November 2009
June 2009
February 2009
Version
Changes
■ Updated Table 3–1.
3.2
■ Updated “Byte Enable Support” and “Mixed-Port Read-During-Write Mode” sections.
■ Updated Table 3–1.
3.1 ■ Updated the “Mixed-Port Read-During-Write Mode” section.
■ Minor text edits.
■ Updated for the Quartus II software version 10.1 release.
■ Added Arria II GZ devices information.
■ Updated Table 3–1 and Table 3–2.
■ Updated Figure 3–10, Figure 3–12, and Figure 3–16.
3.0
■ Added Table 3–6 and Table 3–8.
■ Added Figure 3–10, Figure 3–15, Figure 3–21, Figure 3–23, and Figure 3–24.
■ Added “Error Correction Code Support” section.
■ Minor text edit.
Updated for Arria II GX v9.1 release:
■ Updated Table 3–2
2.0
■ Updated Figure 3–16
■ Minor text edit
■ Updated Table 3–1
■ Updated “Byte Enable Support”, “Simple Dual-Port Mode”, and “Read and Write Clock
Mode” sections
1.1
■ Updated Figure 3–1, Figure 3–2, Figure 3–5, Figure 3–9, Figure 3–12, Figure 3–18,
Figure 3–19, and Figure 3–20
■ Added Figure 3–2, Figure 3–6, Figure 3–10, and Figure 3–13
1.0 Initial release
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration