EP2AGX95EF29C6N Datasheet, PDF (265/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
8–19
Soft CDR Mode
Figure 8–15 shows the soft CDR mode datapath block diagram. In soft CDR mode, the
PLL uses the local clock source as the reference clock. The reference clock must be a
differential signal. The DPA circuitry continuously changes its phase to track the parts
per million (ppm) difference between the upstream transmitter and the local receiver
reference input clocks. Use the DPA_diffioclk clock for bit-slip operation and
deserialization. The DPA_diffioclk clock is divided by the deserialization factor to
produce the rx_divfwdclk clock, which is then forwarded to the FPGA fabric. The
receiver output data (rx_out) to the FPGA fabric is synchronized to this clock. The
parallel clock rx_outclock, generated by the center/corner PLL, is also forwarded to
the FPGA fabric.
Figure 8–15. Receiver Datapath in Soft CDR Mode (Note 1), (2), (3)
rx_out
10
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
FPGA
Fabric
rx_divfwdclk
rx_outclock
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock
Multiplexer
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed
Data
DIN
DPA Clock
3 _{(DPA_LOAD_EN,}
DPA_diffioclk,
rx_divfwdclk)
(LVDS_LOAD_EN,
3 _{LVDS_diffioclk,}
rx_outclk)
PLL (4)
rx_inclock
Notes to Figure 8–15:
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration