EP2AGX95EF29C6N Datasheet, PDF (58/380 Pages) Altera Corporation – Device Interfaces and Integration

3–10
Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Memory Modes
Arria II memory blocks allow you to implement fully synchronous SRAM memory in
multiple modes of operation. M9K and M144K blocks do not support asynchronous
memory (unregistered inputs). MLABs support asynchronous (flow-through) read
operations.
Depending on which memory block you target, you can use the following modes:
■ “Single-Port RAM Mode” on page 3–10
■ “Simple Dual-Port Mode” on page 3–12
■ “True Dual-Port Mode” on page 3–15
■ “Shift-Register Mode” on page 3–17
■ “ROM Mode” on page 3–18
■ “FIFO Mode” on page 3–18
1 To choose the desired read-during-write behavior, set the read-during-write behavior
to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager
in the Quartus II software. For more information about this behavior, refer to
“Read-During-Write Behavior” on page 3–21.
1 When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or hold
time on any of the memory block input registers. This applies to both read and write
operations.
Single-Port RAM Mode
All memory blocks support single-port mode. Single-port mode allows you to do
either a one-read or a one-write operation at a time. Simultaneous reads and writes
are not supported in single-port mode. Figure 3–9 shows the single-port RAM
configuration.
Figure 3–9. Single-Port Memory (Note 1)
data[ ]
address[ ]
wren
byteena[]
addressstall
inclock
clockena
rden
aclr
q[]
outclock
Note to Figure 3–9:
(1) You can implement two single-port memory blocks in a single M9K and M144K blocks. For more information, refer
to “Packed Mode Support” on page 3–5.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation