EP2AGX95EF29C6N Datasheet, PDF (252/380 Pages) Altera Corporation – Device Interfaces and Integration

8–6
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Locations of the I/O Banks
Table 8–2. LVDS Channels Supported in Arria II GX Device Column I/O Banks (Note 1), (2), (3), (4), (5), (6) (Part 2 of
2)
Device
358-Pin FlipChip UBGA 572-Pin FlipChip FBGA 780-Pin FlipChip FBGA 1152-Pin FlipChip FBGA
EP2AGX260
—
—
57(R_D or eTx) +
56(Rx, Tx, or eTx)
97(R_D or eTx) +
96(Rx, Tx, or eTx)
Notes to Table 8–2:
(1) There are no dedicated SERDES and DPA circuitry in device column I/O banks.
(2) R_D = True LVDS input buffers with R_D OCT support.
(3) Rx = True LVDS input buffers without R_D OCT support.
(4) Tx = True LVDS output buffers.
(5) eTx = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
Table 8–3 and Table 8–4 list the maximum number of row and column LVDS I/Os
supported in Arria II GZ devices.
Table 8–3. LVDS Channels Supported in Arria II GZ Device Row I/O Banks (Note 1), (2), (3)
Device
780-Pin FineLine BGA 1152-Pin FineLine BGA 1517-Pin FineLine BGA
EP2AGZ225
—
42(Rx or eTx) +
44(Tx or eTx)
86(Rx or eTx) +
88(Tx or eTx)
EP2AGZ300
—
42(Rx or eTx) +
44(Tx or eTx)
86(Rx or eTx) +
88(Tx or eTx)
EP2AGZ350
—
42(Rx or eTx) +
44(Tx or eTx)
86(Rx or eTx) +
88(Tx or eTx)
Notes to Table 8–3:
(1) Rx = true LVDS input buffers with R_D OCT, Tx = true LVDS output buffers, eTx = emulated LVDS output buffers (either
LVDS_E_1R or LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device, except for the devices
in the 780-pin Fineline BGA. These devices have the LVDS Rx and Tx located on the left side of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
Table 8–4. LVDS Channels Supported in Arria II GZ Device Column I/O Banks (Note 1), (2), (3)
Device
EP2AGZ225
EP2AGZ300
EP2AGZ350
780-Pin FineLine BGA
—
68(Rx or eTx) + 72 eTx
68(Rx or eTx) + 72 eTx
1152-Pin FineLine BGA
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
1517-Pin FineLine BGA
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
Notes to Table 8–4:
(1) Rx = true LVDS input buffers without R_D OCT, eTx = emulated LVDS output buffers (either LVDS_E_1R or
LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the top and bottom sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation