EP2AGX95EF29C6N Datasheet, PDF (126/380 Pages) Altera Corporation – Device Interfaces and Integration

5–18
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–15 shows the external PLL output clock control block.
Figure 5–15. External PLL Output Clock Control Block Arria II Devices
PLL Counter
Outputs and m Counter
n (1)
Static Clock Select (2)
Enable/
Disable
Internal
Logic
IOE (3)
Internal
Logic
Static Clock
Select (2)
PLL<#>_CLKOUT pin
Notes to Figure 5–15:
(1) For Arria II GX devices, n = 8; for Arria II GZ devices, n = 8 or 11.
(2) When the device is in user mode, you can only set the clock select signals through a configuration file
(.sof or .pof). You cannot dynamically control the clock.
(3) The clock control block feeds a multiplexer in the PLL<#>_CLKOUT pin’s IOE. The PLL<#>_CLKOUT pin is a
dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
Clock Enable Signals
Figure 5–16 shows how the clock enable/disable circuit of the clock control block is
implemented in Arria II devices.
Figure 5–16. clkena Implementation for Arria II Devices
(1)
(1)
(2)
clkena
output of clock
select multiplexer
DQ
DQ
R1
R2
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
Notes to Figure 5–16:
(1) The R1 and R2 bypass paths are not available for PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation