EP2AGX95EF29C6N Datasheet, PDF (314/380 Pages) Altera Corporation – Device Interfaces and Integration

9–28
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device’s nCE pin, which prompts the
second device to begin configuration. The second device in the chain begins
configuration in one clock cycle. Therefore, the transfer of data destinations is
transparent to the MAX II device or microprocessor. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
Because all nSTATUS and CONF_DONE pins are tied together, if any device detects an
error, configuration stops for the entire chain and you must reconfigure the entire
chain. For example, if the first device flags an error on nSTATUS, it resets the chain by
pulling its nSTATUS pin low. This behavior is similar to a single device detecting an
error.
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the chain. Configuration
signals can require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices start and complete
configuration at the same time.
Figure 9–12 shows a multi-device PS configuration when both Arria II devices are
receiving the same configuration data.
Figure 9–12. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Memory
ADDR DATA[0]
External Host
(MAX II Device or
Microprocessor)
(1) (1) (2)
10 kΩ
10 kΩ 10 kΩ
GND
Arria II Device
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(3)
N.C.
DATA[0]
nCONFIG
DCLK
GND
Arria II Device
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
DATA[0]
nCONFIG
DCLK
(3)
N.C.
Notes to Figure 9–12:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V_CCIO pin.
For Arria II GZ devices, use the V_CCPGM pin. V_CCIO/V_CCPGM must be high enough to meet the V_IH specification of the I/O on both the device and the
external host. Altera recommends powering up the configuration system I/Os with V_CCIO/V_CCPGM.
(2) A pull-up resistor to V_CCIO/V_CCPGM or a pull-down resistor keeps the nCONFIG line in a known state when the external host is not driving the line.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0]for an Arria II GX device, refer
to Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation