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| EP2AGX95EF29C6N Datasheet, PDF (220/380 Pages) Altera Corporation – Device Interfaces and Integration | |||
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7â18
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7â15. Number of DQ/DQS Groups per Bank in EP2AGZ300 and EP2AGZ350 Devices in the 1517-Pin FineLine BGA
Package (Note 1), (2), (3)
DLL0
I/O Bank 8A
40 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=1 (5)
I/O Bank 8B
24 User I/Os
Ã4=4
Ã8/Ã9=2
Ã16/Ã18=1
I/O Bank 8C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
I/O Bank 7C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16//Ã18=0
I/O Bank 7B I/O Bank 7A
40 User I/Os
24 User I/Os
Ã4=6
Ã4=4
Ã8/Ã9=3
Ã8/Ã9=2 Ã16/Ã18=1
Ã16/Ã18=1 Ã32/Ã36=1 (5)
DLL3
I/O Bank 1A
48 User I/Os
Ã4=7
Ã8/Ã9=3
Ã16/Ã18=1
I/O Bank 6A
48 User I/Os
Ã4=7
Ã8/Ã9=3
Ã6/Ã18=1
I/O Bank 1C
42 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
I/O Bank 2C
42 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
EP2AGZ300 and EP2AGZ350 Devices
in the 1517-Pin FineLine BGA
I/O Bank 6C
42 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
I/O Bank 5C
42 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
I/O Bank 2A
48 User I/Os
Ã4=7
Ã8/Ã9=3
Ã16/Ã18=1
DLL1
I/O Bank 3A
40 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=1 (5)
I/O Bank 3B
24 User I/Os
Ã4=4
Ã8/Ã9=2
Ã16/Ã18=1
I/O Bank 3C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
I/O Bank 4C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
I/O Bank 4B I/O Bank 4A
24 User I/Os
Ã4=4
Ã8/Ã9=2
Ã16/Ã18=1
40 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=1 (5)
I/O Bank 5A
48 User I/Os
Ã4=7
Ã8/Ã9=3
Ã6/Ã18=1
DLL2
Notes to Figure 7â15:
(1) You can also use DQS/DQSn pins in some of the Ã4 groups as RUP and RDN pins, but you cannot use a Ã4 group for memory interfaces if two pins
of the Ã4 group are used as RUP and RDN pins for OCT calibration. If two pins of a Ã4 group are used as RUP and RDN pins for OCT calibration, you
can use the Ã16/Ã18 or Ã32/Ã36 groups that include that Ã4 group, however there are restrictions on using Ã8/Ã9 groups that include that Ã4
group.
(2) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(3) You can also use some of the DQ/DQS pins in I/O Bank 1C as configuration pins. You cannot use a Ã4 DQ/DQS group with any of its pin members
used for configuration purposes. Ensure that the DQ/DQS groups that you have chosen are not also used for configuration because you may lose
up to four Ã4 DQ/DQS groups, depending on your configuration scheme.
(4) These Ã32/Ã36 DQ/DQS groups have 40 pins instead of 48 pins per group.
The DQS and DQSn pins are listed in the Arria II pin tables as DQSXY and DQSnXY,
respectively, where X denotes the DQ/DQS grouping number and Y denotes whether
the group is located on the top (T), bottom (B), left (L), or right (R) side of the device.
The DQ/DQS pin numbering is based on Ã4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T), bottom
(B), left (L), or right (R) side of the device. For example, DQS3B indicates a DQS pin that
is located on the bottom side of the device. The DQ pins belonging to that group are
shown as DQ3B in the pin table. For DQS pins in Arria II GX I/O banks, refer to
Figure 7â16. For DQS pins in Arria II GZ I/O banks, refer to Figure 7â17.
1 The parity, DM, BWSn, NWSn, QVLD, and ECC pins are shown as DQ pins in the pin
table.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation
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