EP2AGX95EF29C6N Datasheet, PDF (125/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
5–17
f For more information, refer to the Clock Control Block (ALTCLKCTRL) Megafunction
User Guide.
Figure 5–13 and Figure 5–14 show the RCLK select blocks.
Figure 5–13. RCLK Control Block for Arria II GX Devices
PLL Counter
Outputs
CLK
Pin
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Note to Figure 5–13:
(1) This clock select signal can only be statically controlled through a configuration file (.sof or .pof) and cannot be
dynamically controlled during user mode operation.
Figure 5–14. RCLK Control Block for Arria II GZ Devices
PLL Counter
Outputs
CLKp CLKn
Pin Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 5–14:
(1) When the device is in user mode, you can only set the clock select signals through a configuration file
(.sof or .pof). You cannot dynamically control the clock.
(2) The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration