EP2AGX95EF29C6N Datasheet, PDF (251/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
8–5
Locations of the I/O Banks
1 Dedicated SERDES and DPA circuitry are only available on the right side of the device
in row I/O banks. SERDES with DPA receivers are only available on differential pins
in the row I/O banks and SERDES transmitters are only available on transmit (Tx)
pins in the row I/O banks. The receive (Rx) pins in row I/O banks are receiver
channels without dedicated SERDES and DPA circuitry.
Table 8–1. LVDS Channels Supported in Arria II GX Device Row I/O Banks (Note 1), (2), (3), (4), (5), (6)
Device
EP2AGX45
EP2AGX65
358-Pin FlipChip UBGA
8(R_D or eTx) +
8(Rx, Tx or eTx)
8(R_D or eTx) +
8(Rx, Tx, or eTx)
EP2AGX95
—
EP2AGX125
—
572-Pin FlipChip FBGA
24(R_D or eTx) +
24(Rx, Tx, or eTx)
24(R_D or eTx) +
24(Rx, Tx, or eTx)
24(R_D or eTx) +
24(Rx, Tx or eTx)
24(R_D or eTx) +
24(Rx, Tx or eTx)
EP2AGX190
—
—
EP2AGX260
—
—
780-Pin FlipChip FBGA
28(R_D or eTx) +
28(Rx, Tx, or eTx)
28(R_D or eTx) +
28(Rx, Tx or eTx)
28(R_D or eTx) +
28(Rx, Tx or eTx)
28(R_D or eTx) +
28((Rx, Tx or eTx)
28(R_D or eTx)+
28(Rx, Tx or eTx)
28(R_D or eTx) +
28(Rx, Tx or eTx)
1152-Pin FlipChip FBGA
—
—
32(R_D or eTx) +
32(Rx, Tx, or eTx)
32(R_D or eTx) +
32(Rx, Tx or eTx)
48(R_D or eTx) +
48(Rx, Tx or eTx)
48(R_D or eTx) +
48(Rx, Tx or eTx)
Notes to Table 8–1:
(1) Dedicated SERDES and DPA circuitry only exist on the right side of the device in the Row I/O banks.
(2) R_D = True LVDS input buffers with R_D OCT support and dedicated SERDES receiver channel with DPA circuitry.
(3) Rx = True LVDS input buffers without R_D OCT support and dedicated SERDES receiver channel with DPA circuitry.
(4) Tx = True LVDS output buffers and dedicated SERDES transmitter channel.
(5) eTx = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
Table 8–2. LVDS Channels Supported in Arria II GX Device Column I/O Banks (Note 1), (2), (3), (4), (5), (6) (Part 1 of
2)
Device
EP2AGX45
EP2AGX65
EP2AGX95
358-Pin FlipChip UBGA
25(R_D or eTx) +
24(Rx, Tx, or eTx)
25(R_D or eTx) +
24(Rx, Tx, or eTx)
—
EP2AGX125
—
EP2AGX190
—
572-Pin FlipChip FBGA
33(R_D or eTx) +
32(Rx, Tx, or eTx)
33(R_D or eTx) +
32(Rx, Tx, or eTx)
33(R_D or eTx) +
32(Rx, Tx, or eTx)
33(R_D or eTx) +
32(Rx, Tx, or eTx)
—
780-Pin FlipChip FBGA
57(R_D or eTx) +
56(Rx, Tx, or eTx)
57(R_D or eTx) +
56(Rx, Tx, or eTx)
57(R_D or eTx) +
56(Rx, Tx, or eTx)
57(R_D or eTx) +
56(Rx, Tx, or eTx)
57(R_D or eTx) +
56(Rx, Tx, or eTx)
1152-Pin FlipChip FBGA
—
—
73(R_D or eTx) +
72(Rx, Tx, or eTx)
73(R_D or eTx) +
72(Rx, Tx, or eTx)
97(R_D or eTx) +
96(Rx, Tx, or eTx)
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration