EP2AGX95EF29C6N Datasheet, PDF (260/380 Pages) Altera Corporation – Device Interfaces and Integration

8–14
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes
channel-to-channel skew on the received serial data streams. If you enabled the DPA
block, the received data is captured with different clock phases on each channel and
might cause the received data to be misaligned from channel to channel. To
compensate for the channel-to-channel skew and establish the correct received word
boundary at each channel, each receiver channel has a dedicated data realignment
circuit that realigns the data by inserting bit latencies into the serial stream.
An optional signal (rx_channel_data_align) controls the bit insertion of each receiver
independently controlled from the internal logic. The data slips one bit on the rising
edge of rx_channel_data_align. The following are requirements for the
rx_channel_data_align signal:
■ An edge-triggered signal
■ The minimum pulse width is one period of the parallel clock in the logic array
■ The minimum low time between pulses is one period of the parallel clock
■ Holding rx_channel_data_align does not result in extra slips
■ Valid data is available two parallel clock cycles after the rising edge of the
rx_channel_data_align signal
Figure 8–10 shows receiver output after a one bit-slip pulse with the deserialization
factor set to 4.
Figure 8–10. Data Realignment Timing
rx_inclock
rx_in
rx_outclock
rx_channel_data_align
rx_out
32 10 32 10 32 10
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set to equal to or greater than the deserialization factor, allowing enough depth in
the word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the ALTLVDS megafunction. An optional status signal
(rx_cda_max) is available to the FPGA fabric from each channel to indicate when the
preset rollover point is reached.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation