EP2AGX95EF29C6N Datasheet, PDF (46/380 Pages) Altera Corporation – Device Interfaces and Integration

2–16
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
Register Chain
In addition to general routing outputs, the ALMs in any given LAB have register
chain outputs to allow registers in the same LAB to be cascaded together. The register
chain interconnect allows a LAB to use LUTs for a single combinational function and
the registers to be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect resources (refer
to Figure 2–14). The Quartus II Compiler automatically takes advantage of these
resources to improve utilization and performance.
Figure 2–14. Register Chain in an LAB (Note 1)
Combinational
Logic
adder0
adder1
reg_chain_in
From previous ALM
in the LAB
labclk
To general or
local routing
DQ
To general or
local routing
reg0
DQ
reg1
To general or
local routing
To general or
local routing
Combinational
Logic
adder0
adder1
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
reg_chain_out
To next ALM
in the LAB
Note to Figure 2–14:
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.
1 For more information about register chain interconnect, refer to “ALM Interconnects”
on page 2–17.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation