EP2AGX95EF29C6N Datasheet, PDF (141/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–33
Figure 5–29 shows an example waveform of the PLL clocks’ phase relationship in
ZDB mode.
Figure 5–29. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode for Arria II Devices
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs (1)
Note to Figure 5–29:
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In external feedback mode, the external feedback input pin (fbin) is phase-aligned
with the clock input pin, as shown in Figure 5–30. Aligning these clocks allows you to
remove clock delay and skew between devices. This mode is supported on all
Arria II GZ PLLs.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) becoming part of the feedback loop. Also, use
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
You must use the same I/O standard on the input clock, feedback input, and output
clocks. Left and right PLLs support this mode when using single-ended I/O
standards only.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration