EP2AGX95EF29C6N Datasheet, PDF (231/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
7–29
For Arria II GZ devices, the reference clock for each DLL may come from PLL output
clocks or any of the two dedicated clock input pins located in either side of the DLL.
Table 7–7 through Table 7–9 show the available DLL reference clock input resources
for the Arria II GZ devices.
Table 7–7. DLL Reference Clock Input for EP2AGZ300 and EP2AGZ350 Devices in the 780-Pin FineLine BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN (Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right)
—
PLL_T1
—
—
PLL_B1
—
—
PLL_B2
—
—
PLL_T2
—
PLL (Corner)
—
—
—
—
Table 7–8. DLL Reference Clock Input for EP2AGZ225, EP2AGZ300, and EP2AGZ350 Devices in the 1152-Pin FineLine
BGA Package (Part 1 of 2)
DLL
DLL0
DLL1
CLKIN (Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLKIN (Left/Right)
CLK0P
CLK1P
CLK0P
CLK1P
PLL (Top/Bottom)
PLL_T1
PLL_B1
PLL (Left/Right)
PLL_L2
—
PLL (Corner)
—
—
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration