EP2AGX95EF29C6N Datasheet, PDF (329/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Device Configuration Pins
9–43
Table 9–16. Dedicated Configuration Pins on the Arria II Device (Part 4 of 4)
Pin Name
DATA0 (2)
DATA[7..1]
User Mode
Configuration
Scheme
N/A
PS, FPP, AS
Parallel
I/O
configuration
schemes
(FPP)
Pin Type
Input
Inputs
Description
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on the
DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor that is
always active.
For Arria II GX devices, DATA0 is a dedicated pin that is used
for both PS and AS configuration modes and is not available
as a user I/O pin after configuration.
For Arria II GZ devices, after PS or FPP configuration, DATA0
is available as a user I/O pin. The state of this pin depends on
the Dual-Purpose Pin settings.
Data inputs. Byte-wide configuration data is presented to the
target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tri-stated.
After FPP configuration, DATA[7..1] are available as user
I/O pins. The state of these pin depends on the
Dual-Purpose Pin settings.
Notes to Table 9–16:
(1) Arria II GZ devices do not support the 3.3-V I/O standard.
(2) To tri-state the AS configuration pins in user mode, turn on the Enable input tri-state on active configuration pins in user mode option from
the Device and Pin Options dialog box in the Configuration tab. This tri-states the DCLK, DATA0, nCSO, and ASDO pins.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration