EP2AGX95EF29C6N Datasheet, PDF (60/380 Pages) Altera Corporation – Device Interfaces and Integration

3–12
Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Figure 3–11 shows the timing waveforms for read and write operations in single-port
mode with unregistered outputs for the MLAB. The rising clock edges trigger the read
operation whereas the falling clock edges triggers the write operation.
Figure 3–11. Timing Waveform for Read-Write Operations for MLABs (Single-Port Mode)
clk_a
wrena
rdena
address_a
a0
a1
data_a
q_a (asynch)
A
B
a0
A
(old data)
C
D
E
F
B
C
a1
(old data)
D
E
Simple Dual-Port Mode
All memory blocks support simple dual-port mode. Simple dual-port mode allows
you to perform one-read and one-write operation to different locations at the same
time. The write operation occurs on port A; the read operation occurs on port B.
Figure 3–12 shows a simple dual-port configuration. Simple dual-port RAM supports
input and output clock mode in addition to the read and write clock mode.
Figure 3–12. Arria II Simple Dual-Port Memory
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
rdaddress[ ]
rden
q[ ]
rd_addressstall
rdclock
rdclocken
ecc_status (1)
Note to Figure 3–12:
(1) Only available for Arria II GZ devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation