EP2AGX95EF29C6N Datasheet, PDF (50/380 Pages) Altera Corporation – Device Interfaces and Integration

3–2
Chapter 3: Memory Blocks in Arria II Devices
Memory Features
Memory Features
Table 3–1 lists the features supported by the embedded memory blocks.
Table 3–1. Summary of Memory Features in Arria II Devices (Part 1 of 2)
Feature
Maximum performance
Total RAM bits (including parity
bits)
Configurations (depth × width)
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed width
support
True dual-port mixed width
support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register clears
Write/Read operation triggering
Same-port read-during-write
MLABs
Arria II GX
500 MHz
Arria II GZ
500 MHz
640
640
64 × 8
64 × 9
64 × 10
32 × 16
32 × 18
32 × 20
64 × 8
64 × 9
64 × 10
32 × 16
32 × 18
32 × 20
v
v
v
v
—
—
v
v
v
v
v
v
—
—
v
v
v
v
v
v
—
—
M9K Blocks
Arria II GX
390 MHz
Arria II GZ
540 MHz
9,216
9,216
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
512 × 16
512 × 18
256 × 32
256 × 36
v
v
v
v
v
v
v
v
v
v
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
512 × 16
512 × 18
256 × 32
256 × 36
v
v
v
v
v
v
v
v
v
v
v
v
M144K Blocks
Arria II GZ
500 MHz
147,456
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
v
v
v
v
v
v
v
v
v
v
v
—
—
v
v
v
v
v
v
v
Outputs cleared if registered,
otherwise reads memory
contents.
Output registers
Write: Falling clock edges.
Read: Rising clock edges
Outputs set to Outputs set
old data to don’t care
v
v
v
v
Outputs cleared
Output registers
Write and Read: Rising clock
edges
Outputs set to old data or
new data
v
v
Outputs cleared
Output registers
Write and Read: Rising
clock edges
Outputs set to old data or
new data
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation