EP2AGX95EF29C6N Datasheet, PDF (119/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
5–11
Clock Network Sources
In Arria II GX devices, clock input pins, internal logic, transceiver clocks, and PLL
outputs can drive the GCLK and RCLK networks, while in Arria II GZ devices, clock
input pins, PLL outputs, and internal logic can drive the GCLK and RCLK networks.
Table 5–2 through Table 5–5 on page 5–13 list the connectivity between the dedicated
clock pins and the GCLK and RCLK networks.
Dedicated Clock Inputs Pins
CLK pins can either be differential clocks or single-ended clocks. Arria II GX devices
support six differential clock inputs or 12 single-ended clock inputs, while Arria II GZ
devices support 16 differential clock inputs or 32 single-ended clock inputs. You can
also use the dedicated clock input pins CLK[4..15] (for Arria II GX devices) and
CLK[15..0] (for Arria II GZ devices) for high fan-out control signals such as
asynchronous clears, presets, and clock enables for protocol signals such as TRDY and
IRDY for PCI Express^® (PCIe^®) through GCLK or RCLK networks.
Logic Array Blocks
You can drive up to four signals into each GCLK and RCLK network with logic array
block (LAB)-routing to allow internal logic to drive a high fan-out, low-skew signal.
1 You cannot drive Arria II PLLs by internally generated GCLKs or RCLKs. The input
clock to the PLL has to come from dedicated clock input pins or PLL-fed GCLKs and
RCLKs only.
PLL Clock Outputs
Table 5–2 and Table 5–3 list the connection between the dedicated clock input pins
and GCLKs.
Table 5–2. Clock Input Pin Connectivity to GCLK Networks for Arria II GX Devices
CLK (p/n Pins)
Clock Resources
4
5
6
7
8
9
10 11 12 13 14 15
GCLK[0..3] (1) — — — — — — — — — — — —
GCLK[4..7]
v v v v— — — — — — — —
GCLK[8..11]
————
v v v v— — — —
GCLK[12..15]
————————
vvvv
Note to Table 5–2:
(1) GCLK[0..3] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX device.
Table 5–3. Clock Input Pin Connectivity to the GCLK Networks for Arria II GZ Devices (Part 1 of 2)
Clock Resources
GCLK[0..3]
GCLK[4..7]
CLK (p/n Pins)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
v v v v— — — — — — — — — — — —
— — — — v v v v— — — — — — — —
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration