EP2AGX95EF29C6N Datasheet, PDF (82/380 Pages) Altera Corporation – Device Interfaces and Integration

4–6
Chapter 4: DSP Blocks in Arria II Devices
Simplified DSP Operation
The combination of a fast, low-latency four-multiplier adder unit and the “chained
cascade” capability of the output chaining adder provides the optimal FIR and vector
multiplication capability.
To support single-channel type FIR filters efficiently, you can configure one of the
multiplier input registers to form a tap delay line input, saving resources and
providing higher system performance.
Figure 4–4. Output Cascading Feature for FIR Structures
From Previous Half-DSP Block
44
Input ¹⁴⁴
Data
44
Result[]
Half-DSP Block
44
To Next
Half-DSP Block
Figure 4–4 shows the optional rounding and saturation unit. This unit provides a set
of commonly found arithmetic rounding and saturation functions in signal
processing.
In addition to the independent multipliers and sum modes, you can use DSP blocks to
perform shift operations. DSP blocks can dynamically switch between logical shift
left/right, arithmetic shift left/right, and rotation operation in one clock cycle.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation