EP2AGX95EF29C6N Datasheet, PDF (173/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
6–9
I/O Banks
In Arria II devices, the maximum number of I/O banks per side, excluding the
configuration banks, is either four or six, depending on the device density. All Arria II
devices support migration across device densities and packages. When migrating
between devices with a different number of I/O banks per side, it is the "B" bank that
is removed or inserted. For example, when moving from a 12-bank device to an
8-bank device, the banks that are dropped are "B" banks, namely: 3B, 5B, 6B, and 8B.
Similarly, when moving from an 8-bank device to a 12-bank device, the banks that are
added are "B" banks, namely: 3B, 5B, 6B, and 8B.
During migration from a smaller device to a larger device, the bank size increases or
remains the same but never decreases. Table 6–5 and Table 6–6 list the pin migration
across device densities and packages.
Table 6–5. Pin Migration Across Densities in Arria II GX Devices (Note 1)
Package Pin Type
Device
EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260
358-pin
Flip Chip
UBGA
I/O
Clock
XCVR channel
144
144
—
—
—
—
12
12
—
—
—
—
4
4
—
—
—
—
572-pin
Flip Chip
FBGA
I/O
Clock
XCVR channel
240
240
248
248
—
—
12
12
12
12
—
—
8
8
8
8
—
—
780-pin
Flip Chip
FBGA
I/O
Clock
XCVR channel
352
352
360
360
360
360
12
12
12
12
12
12
8
8
12
12
12
12
1152-pin
Flip Chip
FBGA
I/O
Clock
XCVR channel
—
—
440
440
600
600
—
—
12
12
12
12
—
—
12
12
16
16
Note to Table 6–5:
(1) Each transceiver channel consists of two transmit (Tx) pins, two receive (Rx) pins and a transceiver clock pin.
Table 6–6. Pin Migration Across Densities in Arria II GZ Devices (Note 1) (Part 1 of 2)
Package
Pin Type
EP2AGZ225
Device
EP2AGZ300
EP2AGZ350
I/O
—
780-pin
Clock
—
Flip Chip FBGA
XVCR channel
—
280
280
1
1
16
16
I/O
550
550
550
1152-pin
Clock
4
4
4
Flip Chip FBGA
XVCR channel
16
16
16
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration