EP2AGX95EF29C6N Datasheet, PDF (312/380 Pages) Altera Corporation – Device Interfaces and Integration

9–26
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
f For more information about SRunner, refer to AN 418: SRunner: An Embedded Solution
for EPCS Programming and the source code on the Altera website.
f For more information about programming serial configuration devices, refer to the
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
PS Configuration
You can program a PS configuration of Arria II devices using an intelligent host, such
as a MAX II device or microprocessor with flash memory, or a download cable. In the
PS scheme, an external host (a MAX II device, embedded processor, or host PC)
controls configuration. Configuration data is clocked into the target Arria II device
using the DATA0 pin at each rising edge of DCLK.
1 The Arria II decompression and design security features are available when
configuring your Arria II device using PS mode.
PS Configuration Using a MAX II Device as an External Host
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Arria II device. You can store configuration data in .rbf, .hex, or
.ttf format.
Figure 9–10 shows the configuration interface connections between an Arria II device
and a MAX II device for single device configuration.
Figure 9–10. Single Device PS Configuration Using an External Host
Memory
ADDR DATA[0]
External Host
(MAX II Device or
Microprocessor)
(1) (1) (2)
10 kΩ
10 kΩ 10 kΩ
GND
Arria II Device
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(3)
N.C. (4)
DATA[0]
nCONFIG
DCLK
Notes to Figure 9–10:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V_CCIO pin.
For Arria II GZ devices, use the V_CCPGM pin. V_CCIO/V_CCPGM must be high enough to meet the V_IH specification of the I/O on both the device and the
external host. Altera recommends powering the configuration system I/Os with V_CCIO/V_CCPGM.
(2) A pull-up resistor to V_CCIO/V_CCPGM or a pull-down resistor keeps the nCONFIG line in a known state when the external host is not driving the line.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0]for an Arria II GX device, refer
to Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
(4) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed the nCE pin of the other device.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation