EP2AGX95EF29C6N Datasheet, PDF (140/380 Pages) Altera Corporation – Device Interfaces and Integration

5–32
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Zero-Delay Buffer Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin
for zero delay through the device. You must use the same I/O standard on the input
and output clocks to guarantee clock alignment at the input and output pins.
Zero-delay buffer mode is supported on all Arria II PLLs.
You must instantiate a bidirectional I/O pin in the design to serve as the feedback
path connecting the FBOUT and FBIN ports of the PLL when using Arria II GZ PLLs in
ZDB mode, along with single-ended I/O standards, to ensure phase alignment
between the CLK pin and the external clock output (CLKOUT) pin. The PLL uses this
bidirectional I/O pin to mimic and compensate for the output delay from the clock
output port of the PLL to the external clock output pin.
1 The bidirectional I/O pin that you instantiate in your design must always be assigned
a single-ended I/O standard.
1 Do not place board traces on the bidirectional I/O pin when using ZDB mode, to
avoid signal reflection.
Figure 5–28 shows ZDB mode in Arria II GZ PLLs. You cannot use differential I/O
standards on the PLL clock input or output pins.
Figure 5–28. ZDB Mode in PLLs for Arria II GZ Devices
inclk
÷n
PFD CP/LF VCO
÷C0
÷C1
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
÷m
fbout
fbin
bidirectional
I/O pin
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation