EP2AGX95EF29C6N Datasheet, PDF (115/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–6. PCLK Networks in (EP2AGX95 and EP2AGX125 Devices)
Top Left PLL
PLL_1
CLK[12..15]
Top Right PLL
PLL_2
PCLK[0..12]
Q1 Q2
Q4 Q3
PCLK[43..58]
PLL_5
PLL_6
Center PLLs
CLK[8..11]
PCLK[13..26]
PCLK[27..42]
PLL_4
Bottom Left PLL
CLK[4..7]
PLL_3
Bottom Right PLL
Figure 5–7. PCLK Networks in (EP2AGX190 and EP2AGX260 Devices)
Top Left PLL
CLK[12..15]
PLL_1
Top Right PLL
PLL_2
PCLK[0..8]
PCLK[72..83]
PCLK[9..17]
PCLK[60..71]
PCLK[18..26]
Q1 Q2
Q4 Q3
PLL_5
PLL_6
Center PLLs
CLK[8..11]
PCLK[48..59]
PCLK[27..35]
PCLK[36..47]
PLL_4
Bottom Left PLL
CLK[4..7]
PLL_3
Bottom Right PLL
5–7
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration