EP2AGX95EF29C6N Datasheet, PDF (59/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
3–11
During a write operation, the RAM output behavior is configurable. If you use the
read-enable signal and perform a write operation with the read enable deactivated,
the RAM outputs retain the values they held during the most recent active read
enable. If you activate read enable during a write operation, or if you do not use the
read-enable signal at all, the RAM outputs show the “new data” being written, the
“old data” at that address, or a “don’t care” value.
Table 3–4 lists the possible port width configurations for memory blocks in single-port
mode.
Table 3–4. Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode)
Port Width Configurations
MLABs
64 × 8
64 × 9
64 × 10
32 × 16
32 × 18
32 × 20
M9K Blocks
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
512 × 16
512 × 18
256 × 32
256 × 36
M144K Blocks
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
Figure 3–10 shows timing waveforms for read and write operations in single-port
mode with unregistered outputs for M9K and M144K blocks. Registering the M9K
and M144K block outputs delay the q output by one clock cycle.
Figure 3–10. Timing Waveform for Read-Write Operations for M9K and M144K Blocks (Single-Port Mode)
clk_a
wrena
rdena
address_a
data_a
q_a (asynch)
a0
a1
A
B
C
D
E
F
a0(old data)
A
B
a1(old data)
D
E
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration