EP2AGX95EF29C6N Datasheet, PDF (308/380 Pages) Altera Corporation – Device Interfaces and Integration

9–22
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
AS and Fast AS Configuration (Serial Configuration Devices)
If the configuration bitstream size exceeds the capacity of a serial configuration
device, you must select a larger configuration device, enable the compression feature,
or both. When configuring multiple devices, the size of the bitstream is the sum of the
configuration bitstreams of the individual devices.
A system may have multiple devices that contain the same configuration data. In AS
chains, you can implement this by storing one copy of the SRAM object file (.sof) in
the serial configuration device. The same copy of the .sof configures the master
Arria II device and all remaining slave devices concurrently. All Arria II devices must
be the same density and package.
To configure four identical Arria II devices with the same .sof, you can set up the
chain similar to the example shown in Figure 9–8. The first device is the master device
and its MSEL pins must be set to select AS configuration. The other three slave devices
are set up for concurrent configuration and their MSEL pins must be set to select PS
configuration. The nCE input pins from the master and slave are connected to GND,
and the DATA and DCLK pins connect in parallel to all four devices. During the
configuration cycle, the master device reads its configuration data from the serial
configuration device and transmits the configuration data to all three slave devices,
configuring all of them simultaneously.
Figure 9–8 shows the multi-device AS configuration when the devices receive the
same data using a single .sof.
Figure 9–8. Multi-Device AS Configuration When the Devices Receive the Same Data Using a Single .sof
V_CCIO/V_CCPGM V_CCIO/V_CCPGM V_CCIO/V_CCPGM
(1)
(1)
(1)
Arria II
Device Slave
nSTATUS
CONF_DONE nCEO
N.C.
nCONFIG
nCE
10 kΩ 10 kΩ 10 kΩ
DATA[0]
DCLK
MSEL[n..0]
(2)
Serial Configuration
Device
DATA
DCLK
nCS
ASDI
GND
Arria II
Device Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO N.C.
DATA0
DCLK
nCSO
ASDO
CLKUSR
(3)
MSEL[n..0] (2)
GND
Arria II
Device Slave
nSTATUS
CONF_DONE nCEO
N.C.
nCONFIG
nCE
DATA[0]
DCLK
MSEL[n..0]
(2)
Arria II
Device Slave
nSTATUS
CONF_DONE nCEO
N.C.
nCONFIG
nCE
Buffers (4)
DATA[0]
DCLK
MSEL[n..0]
(2)
Notes to Figure 9–8:
(1) Connect the pull-up resistors to the V_CCIO power supply of I/O bank 3C for Arria II GX devices and to V_CCPGM at a 3.0-V power supply for Arria II GZ
devices.
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
(3) Arria II devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
(4) Connect the repeater buffers between the Arria II master and slave devices for DATA[0] and DCLK. This is to prevent any potential signal integrity
and clock skew problems.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation