EP2AGX95EF29C6N Datasheet, PDF (319/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
JTAG Configuration
9–33
JTAG Configuration
JTAG has developed a specification for boundary-scan testing. This boundary-scan
test (BST) architecture offers the capability to efficiently test components on PCBs
with tight lead spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is operating normally.
You can also use JTAG circuitry to shift configuration data into the device. The
Quartus II software automatically generates .sofs that you can use for JTAG
configuration with a download cable in the Quartus II software programmer.
f For more information about JTAG boundary-scan testing and commands available
using Arria II devices, refer to the following documents:
■ JTAG Boundary-Scan Testing in Arria II Devices chapter
■ Programming Support for Jam STAPL Language
Arria II devices are designed such that JTAG instructions have precedence over any
device configuration modes. Therefore, JTAG configuration can take place without
waiting for other configuration modes to complete. For example, if you attempt JTAG
configuration of Arria II devices during PS configuration, PS configuration is
terminated and JTAG configuration begins.
1 You cannot use the Arria II decompression or design security features if you are
configuring your Arria II device using JTAG-based configuration.
1 A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and
one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the
TDI, TMS, and TRST pins have weak internal pull-up resistors (typically 25 k ). All the
JTAG pins are powered by the V_CCIO power supply of I/O bank 8C for Arria II GX
devices and 2.5-V/3.0-V V_CCPD power supply for Arria II GZ devices. All the JTAG
pins support only the LVTTL I/O standard.
All user I/O pins are tri-stated during JTAG configuration. Table 9–13 lists the
function of each JTAG pin.
f For more information about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the JTAG Boundary-Scan Testing in Arria II
Devices chapter.
Table 9–13. JTAG Pins Signals (Part 1 of 2)
Pin
Name
TDI
TDO
Pin Type
Test data
input
Test data
output
Description
Serial input pin for instructions as well as test and programming data. Data is shifted in on the
rising edge of TCK. If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data. Data is shifted out on
the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. If the
JTAG interface is not required on your board, you can disable the JTAG circuitry by leaving this pin
unconnected.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration