EP2AGX95EF29C6N Datasheet, PDF (266/380 Pages) Altera Corporation – Device Interfaces and Integration

8–20
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Differential I/O Termination
The Arria II device family provides a 100- R_D OCT option on each differential
receiver channel for LVDS standards. OCT saves board space by eliminating the need
to add external resistors on the board. You can enable OCT in the Quartus II software
Assignment Editor.
For Arria II GX devices, OCT is supported in the top, right, and bottom I/O banks.
Arria II GX clock input pins (CLK[4..15]) do not support OCT. For Arria II GZ
devices, R_D OCT is supported on all row I/O pins and dedicated clock input pins
(CLK[0,2,9,11]). It is not supported for column I/O pins and dedicated clock input
pins (CLK[1,3,8,10]).
Figure 8–16 shows LVDS input OCT.
Figure 8–16. LVDS Input Buffer I/O R_D OCT
LVDS
Transmitter
Z₀ = 50 Ω
Z₀ = 50 Ω
Arria II Differential
Receiver with
R_D = 100 Ω OCT
R_D
Table 8–7 lists the assignment name and its value for differential input OCT in the
Quartus II software Assignment Editor.
Table 8–7. Differential Input OCT in Quartus II Software Assignment Editor
Assignment Name
Input Termination (Accepts wildcards/groups)
Assignment Value
Differential
f For more information, refer to I/O Features in Arria II Devices chapter.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation