EP2AGX95EF29C6N Datasheet, PDF (136/380 Pages) Altera Corporation – Device Interfaces and Integration

5–28
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Clock Feedback Modes
Arria II PLLs support up to six different clock feedback modes. Each mode allows
clock multiplication and division, phase shifting, and programmable duty cycle.
Table 5–14 lists the clock feedback modes supported by the Arria II PLLs.
Table 5–14. Clock Feedback Mode Availability for Arria II Devices
Clock Feedback Mode
Availability in Arria II GX Devices
Source-synchronous mode
No-compensation mode
Normal mode
Zero-delay buffer (ZDB) mode (1)
External Feedback (2)
LVDS compensation
Yes
Yes
Yes
Yes
No
Yes (4)
Availability in Arria II GZ Devices
Top/Bottom PLLs
Yes
Yes
Yes
Yes
Yes
No
Left/Right PLLs
Yes
Yes
Yes
Yes
Yes (3)
Yes
Notes to Table 5–14:
(1) ZDB mode uses 8 ns delay for compensation in Arria II GX devices.
(2) The high-bandwidth PLL setting is not supported in the external feedback mode.
(3) External feedback mode is supported for single-ended inputs and outputs only on the left and right PLLs.
(4) LVDS compensation mode is only supported on PLL_2, PLL_3, PLL_5, and PLL_6.
1 Input and output delays are fully compensated by a PLL only when you use the
dedicated clock input pins associated with a given PLL as clock sources. For example,
when you use PLL_1 (Arria II GX devices) or PLL_T1 (Arria II GZ devices) in normal
mode, the clock delays from the input pin to the PLL clock output-to-destination
register are fully compensated, provided the clock input pin is one of the following
four pins: CLK12, CLK13, CLK14, or CLK15. When an RCLK or GCLK network drives the
PLL, the input and output delays may not be fully compensated in the Quartus II
software. Another example is when PLL_1 (Arria II GX devices) or PLL_T2 (Arria II GZ
devices) is configured in zero delay buffer mode and the PLL input is driven by a
dedicated clock input pin, a fully compensated clock path results in zero delay
between the clock input and one of the output clocks from the PLL. If the PLL input is
instead fed by a non-dedicated input (using the GCLK network), the output clock
may not be perfectly aligned with the input clock.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation