EP2AGX95EF29C6N Datasheet, PDF (157/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–49
Figure 5–41 shows the scan chain order of Arria II GX PLL components which have
seven post-scale counters. The reconfiguration bits start with the C6 post-scale
counter.
Figure 5–41. Scan Chain Order of PLL Components for Arria II GX PLLs
DATAIN
LF K CP
N
MSB
LSB
M
C0
C6
C5
C4
C3
C2
C1
DATAOUT
Figure 5–42 shows the scan chain order of PLL components for the top and bottom
Arria II GZ PLLs.
Figure 5–42. Scan Chain Order of PLL Components for Top and Bottom of Arria II GZ PLLs (Note 1)
DATAIN
LF K CP
N
MSB
LSB
M
C0
C6
C5
C4
C3
C2
C1
C7
C8
C9
DATAOUT
Note to Figure 5–43:
(1) The left and right PLLs have the same scan chain order. The post-scale counters end at C6.
Figure 5–43 shows the scan chain bit-order sequence for post-scale counters in all
Arria II PLLs.
Figure 5–43. Scan Chain Bit-Order Sequence for Post-Scale Counters in Arria II PLLs
HB
HB
HB
HB
HB
HB
HB
HB
0
1
2
3
4
5
6
7
rbypass
DATAIN
LB
LB
LB
LB
LB
LB
LB
LB
DATAOUT
0
1
2
3
4
5
6
7
rselodd
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration