EP2AGX95EF29C6N Datasheet, PDF (92/380 Pages) Altera Corporation – Device Interfaces and Integration

4–16
Figure 4–9. 9-Bit Independent Multiplier Mode Shown for Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
9
dataa_0[8..0]
9
datab_0[8..0]
9
dataa_1[8..0]
9
datab_1[8..0]
9
dataa_2[8..0]
9
datab_2[8..0]
9
dataa_3[8..0]
9
datab_3[8..0]
18
result_0[ ]
18
result_1[ ]
18
result_2[ ]
18
result_3[ ]
Half-DSP Block
The multiplier operands can accept signed integers, unsigned integers, or a
combination of both. You can change the signa and signb signals dynamically and
register these signals in the DSP block. Additionally, you can register the multiplier
inputs and results independently. You can use the pipeline registers in the DSP block
to pipeline the multiplier result, increasing the performance of the DSP block.
1 The rounding and saturation logic unit is supported for 18-bit independent multiplier
mode only.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation